The present invention relates to a Schmitt trigger circuit having good hysteresis characteristics.
A conventional Schmitt trigger circuit operates on the basis of different threshold values when an input signal level increases and decreases. The circuit has hysteresis characteristics in changes of the output signal level with respect to changes in the input signal level. Thus, the circuit has a wide noise margin and does not have a tendency to operate erratically, due to noise included in the input signal. For this reason, the circuit is used in converting an input signal having slow leading and trailing edges into an output signal having sharp leading and trailing edges, in accordance with a preset threshold voltage.
FIG. 1 is a circuit diagram of the Schmitt trigger circuit disclosed in Japanese patent publication No. 55-90130. An input signal IN is supplied to one input terminal of a NAND gate 2, through an inverter 1. The input signal IN is also supplied to one input terminal of another NAND gate 3, through two inverters 4, 5 connected in series therewith. The NAND gates 2, 3 cross feed their outputs back to the other input terminal thereof, and thereby constitute an SR flip-flop. Therefore, the output from inverter 1 is a set input S to the flip-flop, and the output from inverter 5 is a reset input R to the flip-flop. An output signal OUT appears at the output terminal of NAND gate 2. With reference to FIG. 1, inverters 1 and 4 have different threshold voltages; with inverter 1 having a high threshold voltage and inverter 4 having a low threshold voltage.
FIG. 2 is a circuit diagram of the CMOS inverter serving as the basic unit of the circuit shown in FIG. 1. Referring to FIG. 2, reference numeral 6 denotes a p-channel MOS transistor and 7 denotes an n-channel MOS transistor. The gates of the transistors 6 and 7 are commonly connected and receive an input voltage Vin. The source of the transistor 6 is connected to a power source voltage Vdd, and the drain thereof is connected to the drain of the transistor 7. An output voltage Vout is produced from the common node of the drain of the transistor 6 and the drain of the transistor 7. The source of the transistor 7 is connected to a GND potential.
In FIG. 3, curve A shows the input voltage (Vin) vs. the output voltage (Vout) characteristics of the CMOS inverter shown in FIG. 2. Referring to this characteristic curve A, when the intersection of the curve with a curve wherein Vin=Vout is defined as a threshold voltage Vt, this voltage Vt is given by the following equation: ##EQU1## where: Vthn: threshold voltage of the n-channel MOS transistor
Vthp: threshold voltage of the p-channel MOS transistor PA1 .beta.n: current amplification factor of the n-channel MOS transistor PA1 .beta.p: current amplification factor of the p-channel MOS transistor.
If we assume that the relationship wherein .beta.p&lt;.beta.n=.infin. holds true in equation (1) above, equation (2) below can be obtained, as follows: EQU Vt=Vthn (2)
A modification of equation (1) yields equation (3), below: ##EQU2##
If we assume that the relationship wherein .beta.n&lt;.beta.p=.infin. holds true in equation (3) above, equation (4) below may be obtained, as follows: EQU Vt=Vdd-.vertline.Vthp.vertline. (4)
Accordingly, in the inverter shown in FIG. 2, the threshold voltage Vt can be freely changed in accordance with the ratio of current amplification factors .beta.n and .beta.p of p and n-channel transistors 6 and 7, respectively. The variable range of the threshold voltage Vt has, as a lower limit, the value Vthn given by equation (2) above; and, as an upper limit, the value Vdd-.vertline.Vthp.vertline. given by equation (4) above, as may be seen from curve B in FIG. 3.
If the channel width is defined as W and the channel length is defined as L, the current amplification factor .beta. of the MOS transistor is proportional to the ratio, W/L. This implies that the current amplification factor .beta. of the MOS transistor can be changed and the threshold voltage Vt of the CMOS inverter can be changed by changing the ratio W/L of the channel width W to the channel length L of the MOS transistor.
In the CMOS inverter shown in FIG. 2, the threshold voltage Vt can be changed in accordance with the current amplification factor .beta. of the MOS transistor. Utilizing this fact, a threshold voltage VtH of the inverter 1 is set to be high, and a threshold voltage VtL of the inverter 4 is set to be low. With this arrangement, as shown in the timing charts in FIG. 4, when the input signal IN gradually rises in level from the GND level, reaches the power source voltage Vdd, and thereafter returns to the GND level, an output S from the inverter 1, an output R from the inverter 5, and an output signal OUT from the flip-flop change in the manner to be described below. The input signal IN rises from time T1 and reaches the threshold voltage VtL at time T2 of the inverter 4, and an output P from the inverter 4 goes from level "H" to level "L" and the output R from the inverter 5 goes from level "L" to "H". When the input signal IN rises further and reaches the threshold voltage VtH at time T3, the outputs S from the inverter 1 goes from level "H" to level "L". The set terminal S of the flip-flop consisting of the NAND gates 2 and 3 is set at level "L", the reset terminal R is set at level "H", and the output signal OUT goes from level "L" to "H".
After the input signal IN further increases to reach the power source voltage Vdd, it decreases and reaches the threshold voltage VtH of the inverter 1 at time T4. Thus, the output from the inverter 1 goes from level "L" to "H" at time T4. The input signal IN further decreases to reach the threshold voltage VtL of the inverter 4, and the output from the inverter 4 goes from level "L" to "H" and the output R from the inverter 5 goes from level "L" to "H". At this time point, the set terminal S of the flip-flop is at level "H" and the reset terminal R thereof is at level "L", and the output signal OUT thereof goes from level "H" to level "L".
A Schmitt trigger circuit consisting of the SR flip-flop and CMOS inverter shown in FIG. 1 can be made to have the hysteresis characteristics which pertain to a change in the output voltage Vout with respect to a change in the input voltage Vin, by using inverters having different threshold voltages.
However, in the Schmitt trigger circuit shown in FIG. 1, each of the three CMOS inverters requires two MOS transistor elements. Furthermore, each of the two NAND gates constituting a flip-flop circuit requires four MOS transistor elements. Thus, the circuit shown in FIG. 1 requires a total of 14 elements.
However, in the semiconductor industry, and especially in the field of integrated circuits, it is desired that the number of elements be reduced to minimize the chip size, reduce the manufacturing cost and improve the manufacturing yield. Since the Schmitt trigger circuit shown in FIG. 1 requires a large number of elements and increases the chip size, it is strongly desired to decrease the number of elements without impairing the performance of the circuit.